1. Field of Invention
The present invention relates to a via structure and its method of manufacture. More particularly, the present invention relates to a process for forming a via that can avoid the formation of re-entrances or notches when the via is not fully aligned with the metal conductive layer.
2. Description of Related Art
As the level of integration for semiconductor devices is increased, the number of metal interconnects linking the devices must correspondingly be increased. To fit all the metal interconnects on the available wafer surface, besides fabricating finer interconnects, several layers of these interconnects are now commonly employed. A via is a semiconductor structure serving as a link between different metallic layers at different height levels. When the dimensions of semiconductor devices are further shrunk, more stringent design rules are required. Consequently, the quality requirements of a via are raised. When there is re-entrances or notches in the via, interconnectivity between different metallic conductive layers will be greatly affected, leading to a lower device reliability.
FIGS. 1A and 1B are side views showing the progression of manufacturing steps for producing a conventional via structure. First, as shown in FIG. IA, a semiconductor device 10 is provided. The semiconductor device has a metallic layer or transistors having source/drain regions and gate regions already formed thereon. The metallic layer or the transistors are represented as a device layer 11 in FIG. 1A. Next, a conductive layer 12 is formed over the device layer 11, for example, by sputtering a metallic layer or an aluminum layer, or by depositing a polysilicon layer. In general, a titanium/titanium nitride (Ti/TiN) composite layer 14, which acts as an anti-reflective coating (ARC) and an etching stop layer, is also formed over the conductive layer 12. Thereafter, photolithographic and etching processes are used to pattern the conductive layer 12 forming the structure as shown in FIG. 1A
Next, as shown in FIG. IB, an inter-metal dielectric (IMD) layer 13 is deposited over the conductive layer 12. The IMD can be, for example, a borophosphosilicate glass (BPSG) layer, a spin-on-glass (SOG) layer or similar types of material layers. Then, using photolithographic and etching processes again, a photoresist layer 15 is formed over the IMD layer 13. Thereafter, the IMD layer 13 is patterned to form openings 16 in designated locations exposing a portion of the conductive layer 12. In the subsequent step, conductive material, for example, tungsten, is deposited into the openings 16 to form via structures for electrically connecting top and bottom metallic layers. Finally, subsequent processes necessary for completing the fabrication of interconnects are conducted.
Normally, the aforementioned photolithographic and photoresist patterning procedures are not error free and can be cause slight misalignment. When subsequent etching is carried out to form the openings 16, the resulting openings are not in exact alignment with the conductive layer 12. Under these circumstances, the side of the conductive layer can be over-etched forming re-entrances or notches such as 17 in FIG. 1B. These re-entrances not only will prevent smooth deposition of the titanium/titanium nitride composite layer in a subsequent process, but will also affect the quality of subsequently deposited metal in the via and leading to poor step coverage. For example, voids can form inside the via leading to a large increase in via resistance, thereby lowering the electrical conductivity as well as the reliability of a device. In addition, the voids in the via will result in a stronger electromigration (EM). EM is a phenomenon that occurs when electrons from a metal are constantly bombarding against certain region, which after some time becomes structurally unstable. EM phenomenon is especially serious at metallic interface regions. Thus, EM is an undesirable side effects in a via structure that needs to be eliminated.
Aside from forming voids in the via, the conventional method of forming a via has some other defects as well. For example, the titanium/titanium nitride composite layer 14 that forms over the conductive layer can serve as an anti-reflection coating as well as an etching stop layer. However, the existence of a titanium/titanium nitride composite layer 14 can easily lead to a high and non-uniform via resistance due to Rv scattering. Furthermore, the layer 14 enhances the misalignment problem when a photolithographic alignment is performed. Hence, etching operation becomes more difficult to control and further miniaturization of devices is more difficult to accomplish.
In light of the foregoing, there is a need to provide an improved method for forming a via.